• DocumentCode
    709867
  • Title

    ESD protection clamp with active feedback and mis-trigger immunity in 28nm CMOS process

  • Author

    Parthasarathy, Srivatsan ; Salcedo, Javier A. ; Herrera, Sandro ; Hajjar, Jean-Jacques

  • Author_Institution
    Analog Devices, Inc., Wilmington, MA, USA
  • fYear
    2015
  • fDate
    19-23 April 2015
  • Abstract
    Data Converters in 28nm CMOS processes have the need to support higher voltage power supply domains in addition to the more traditional core and I/O voltages. In this work a new supply clamp architecture is proposed which ensures a reliable low leakage performance at the higher supply voltages (2.5V/3.3V). An active feedback network is designed into the supply clamp architecture to ensure uniform clamping during the duration of the ESD event. Miss-trigger immunity and over voltage protection is additionally incorporated to ensure reliable functionality up to 3.3V and across all the process corners.
  • Keywords
    CMOS integrated circuits; electrostatic discharge; overvoltage protection; CMOS process; ESD protection clamp; active feedback network; clamp architecture; miss-trigger immunity; overvoltage protection; size 28 nm; voltage 2.5 V; voltage 3.3 V; Clamps; Current measurement; Electrostatic discharges; Logic gates; MOS devices; Resistors; Transmission line measurements; 28nm and ESD; CDM; SOC;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium (IRPS), 2015 IEEE International
  • Conference_Location
    Monterey, CA
  • Type

    conf

  • DOI
    10.1109/IRPS.2015.7112794
  • Filename
    7112794