DocumentCode
709875
Title
Employing transistor reliability testing as an FA tool for understanding HTOL product BIST failures
Author
Yassine, Abdullah ; Blair, Lauren ; Seifert, Wayland
Author_Institution
Device Anal. Lab., Adv. Micro Devices, Inc., Austin, TX, USA
fYear
2015
fDate
19-23 April 2015
Abstract
We observed large Vmin shift on products produced using 28nm process during high temperature operating life (HTOL) testing. Failure analysis (FA) revealed that some of the n-channel metal oxide semiconductor field-effect (MOSFET) transistors of the failing cells have very low threshold (Vt) voltages. Those measured Vt values were unexpected and caused concern. In this study, we present the use of transistor reliability testing using nano-probing as an FA tool for understanding the built-in self-test (BIST) failures that we observed on some products during HTOL qualification. The study identified that the Vt shift was due to parametric shift under off-state stress. We found that the off-state stress (Vd = Vs = Vstress and Vg=0) caused the Vt to shift to lower value creating large imbalance in the cells, which caused Vmin failure. A correlation was found between the initial Vt value and the Vt shift. The finding led to employing additional Vmin guardband and changes in the stress pattern used during HTOL stress.
Keywords
MOSFET; built-in self test; failure analysis; life testing; semiconductor device reliability; semiconductor device testing; FA; FA tool; HTOL product BIST failures; MOSFET transistors; built-in self-test; failure analysis; high temperature operating life testing; n-channel metal oxide semiconductor field-effect transistors; nano-probing; off-state stress; size 28 nm; threshold voltages; transistor reliability testing; Built-in self-test; Degradation; Integrated circuit reliability; Random access memory; Stress; Transistors; BIST; BTI; FA; HTOL; SRAM; Vmin failure; Vt shift; failure analysis; nano-probing; off-state stress;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location
Monterey, CA
Type
conf
DOI
10.1109/IRPS.2015.7112802
Filename
7112802
Link To Document