Wafer-level electromigration for reliability monitoring: Quick-turn electromigration stress with correlation to package-level stress

Rapid, accurate and flexible reliability characterization capabilities are important tools in process development and monitoring. Electromigration evaluation has largely relied on packaged test structures given the need for high temperatures to provide sufficient acceleration. However, several Wafer-Level (WL) electromigration (EM) techniques and their correlation to Package-Level (PL) tests have been reported (e.g. SWEAT[1], [2], isothermal[3], tests). Presented in the this paper is a wafer-level electromigration test that addresses the PL correlation issues presented by quick-turn tests, but maintains the advantages of wafer-level and allows quick comparison to PL baseline with a significant advantage in time-to-data over PL-EM testing. Statistical matching of initial resistance (R0) and Time-to-Failure (TTF) between PL vs. WL electromigration tests on two concurrently stressed structures across sixteen reticle locations is demonstrated. This WL-EM stress technique provides equivalent TTF, with no reliance on extrapolations, whilst yielding an advantage in time-to-data relative to standard PL-EM tests.