RTS noise reduction of 1Y-nm floating gate NAND flash memory using process optimization

We report the random telegraph noise characteristics of 1Y-nm floating gate NAND Flash memory and behaviors of random telegraph noise generating traps. The location of selected traps are extracted and their behaviors in different temperature are also investigated. To reduce the threshold voltage fluctuations, we optimize the process conditions of 1Y-nm floating gate NAND Flash memories including tunnel oxide reduction and modification on annealing conditions. We successfully decrease the threshold voltage fluctuations as low as that of 2Y-nm floating gate NAND Flash memories.