DocumentCode :
709888
Title :
Impact of nanoscale polarization relaxation on endurance reliability of one-transistor hybrid memory using combined storage mechanisms
Author :
Yu-Chien Chiu ; Chun-Yen Chang ; Hsiao-Hsuan Hsu ; Chun-Hu Cheng ; Min-Hung Lee
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
fYear :
2015
fDate :
19-23 April 2015
Abstract :
We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 1012-cycling endurance at 85oC. Such excellent endurance reliability at 85°C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.
Keywords :
integrated circuit reliability; random-access storage; charge trapping mechanism; charge-trapping node; combined storage mechanisms; endurance reliability; ferroelectric polarization effect; high-temperature endurance reliability; hybrid nonvolatile memory; memory structure design; nanoscale polarization relaxation impact; one-transistor hybrid memory; program-erase time; temperature 85 degC; temperature-dependent polarization relaxation; threshold voltage window; tight switching margin; time 20 ns; voltage 2 V; Charge carrier processes; Dielectrics; Iron; Logic gates; Nonvolatile memory; Reliability; Switches; charge trapping; endurance; ferroelectric polarization; nonvolatile memory; retention;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/IRPS.2015.7112817
Filename :
7112817
Link To Document :
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