DocumentCode :
709893
Title :
Printed-circuit board (PCB) charge induced product yield-loss during the final test
Author :
Jian-Hsing Lee ; Takahashi, Kunihiko ; Prabhu, Manjunatha ; Natarajan, Mahadeva Iyer
Author_Institution :
GLOBALFOUNDRIES Inc., Malta, NY, USA
fYear :
2015
fDate :
19-23 April 2015
Abstract :
The voltage to damage a chip under the ESD test is often higher than several hundred volts. However, we have observed that the voltage below 6V still can damage the chip to induce the yield-loss of a product in the production line. It is because that the voltage is high enough to damage the components of the low voltage circuits (1.8V), but is still too low to turn on the ESD protection device.
Keywords :
electrostatic discharge; low-power electronics; printed circuit testing; ESD protection device; ESD test; PCB charge-induced product yield-loss; low-voltage circuits; printed-circuit board; voltage 1.8 V; Capacitors; Electrostatic discharges; Electrostatics; Integrated circuit modeling; Logic gates; Resistors; Stress; Electrostatic Discharge (ESD); Printed Circuit Board (PCB); resistor;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Reliability Physics Symposium (IRPS), 2015 IEEE International
Conference_Location :
Monterey, CA
Type :
conf
DOI :
10.1109/IRPS.2015.7112823
Filename :
7112823
Link To Document :
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