Title :
An OpenGL ES 2.0 3D graphics SoC with versatile HW/SW development support
Author :
Hsu-Kang Dow ; Ching-Hua Huang ; Chun-Hung Lai ; Kai-Hsiang Tsao ; Sheng-Chih Tseng ; Kun-Yi Wu ; Ting-Hsuan Wu ; Ho-Chun Yang ; Da-Jing Zhang Jain ; Yun-Nan Chang ; Haga, Steve W. ; Shen-Fu Hsiao ; Ing-Jer Huang ; Shiann-Rong Kuang ; Chung-Nan Lee
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-sen Univ., Kaohsiung, Taiwan
Abstract :
A multi-threaded programmable shader pipeline 3D graphics SoC with support for OpenGL ES 2.0 has been developed and fabricated. The sample chip is ARMv4T compatible with the 3D processing capability of 14.9 Mvertices/s, 3.6 Mpixels/s and up to 4K resolution. The die size is 3.85×3.85 mm2, with 2.96M gates on a TSMC 90nm CMOS 1P9M. This new SoC includes software to support OpenGL ES API libraries, GLSL compilation and simulation. The SoC also comes with various development tools, including GPU simulators for hardware validation, profile assisted compiler optimization and compiler verification. For developers, we also present a QEMU-based simulation platform and SoC Performance Monitoring Tool Suite (PMTS) to assist developers in optimizing the system and detecting performance bottlenecks.
Keywords :
CMOS integrated circuits; computer graphics; microcontrollers; multi-threading; system-on-chip; ARMv4T; GLSL compilation; GPU simulators; OpenGL ES 2.0 3D graphics SoC; OpenGL ES API library; PMTS; QEMU-based simulation platform; SoC performance monitoring tool suite; TSMC CMOS 1P9M; compiler verification; hardware validation; multithreaded programmable shader pipeline 3D graphics SoC; picture size 3.6 Mpixel; profile assisted compiler optimization; size 90 nm; versatile HW-SW development support; Graphics processing units; Hardware; Monitoring; Protocols; System-on-chip; Three-dimensional displays; 3D Computer Graphics; GPU; GPU Simulator; Multi-Core; OpenGL ES; Shading Language Compiler; System-on-Chip;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114496
