A dual-edge sampling CES delay-locked loop based clock and data recovery circuits

Author

Jih-Ren Goh ; Yen-Long Lee ; Soon-Jyh Chang

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

4

Abstract

This paper presents a dual-edge sampling clock-embedded signaling (CES) DLL based CDR. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed method can save 4 times number of the required delay cells compared to the conventional DLL, enhancing the power efficiency and reducing silicon area. The test chip is designed in TSMC 180-nm CMOS process. The core area of the test chip is 0.519*0.137 mm² and the power efficiency of the proposed CDR is 1.43 mW/Gb/s with wide operating range of 0.5 Gb/s to 3.0 Gb/s.

Keywords

CMOS digital integrated circuits; clock and data recovery circuits; delay lock loops; encoding; integrated circuit design; integrated circuit testing; TSMC CMOS process; bit rate 0.5 Gbit/s to 3.0 Gbit/s; clock and data recovery circuits; dual-edge sampling CES DLL-based CDR; dual-edge sampling CES delay-locked loop; half-UI embedded clock coding; power efficiency; silicon area reduction; size 180 nm; Clocks; Delays; Encoding; Hardware; Jitter; Multiplexing; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2015.7114500

Filename

7114500