Title :
All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction
Author :
Yi-Ping Kuo ; Po-Tsang Huang ; Chung-Shiang Wu ; Yu-Jie Liang ; Ching-Te Chuang ; Yuan-Hua Chu ; Wei Hwang
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best (lowest) FOM of 0.76 pA·s can be realized.
Keywords :
CMOS integrated circuits; calibration; circuit tuning; digital control; voltage regulators; PMOS strength self-calibration; TSMC LP CMOS process; all digitally controlled linear voltage regulator; comparator-based error detector; loading current variations; ripple reduction; size 65 nm; timing-detected fine tune; ultra-low-power event-driven sensing platforms; voltage 0.43 V to 0.6 V; voltage-detected coarse tune; Calibration; Clocks; Detectors; Loading; Regulators; Voltage control;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114514
