A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer

This paper presents a comparator-based OTA first-order discrete-time low-distortion sigma-delta modulator. A split data weighted averaging (DWA) algorithm logic is proposed to release the heavy burden of digital circuit while a 6 bit DAC is implemented in this work. In addition, a comparator-based OTA is used to reduce the power consumption. On the top of that, to achieve lower power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. The modulator core occupies an active area of 0.0275 mm² in TSMC 90-nm 1P9M CMOS process. Experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.