Title :
Trinocular adaptive window size disparity estimation algorithm and its real-time hardware
Author :
Akin, Abdulkadir ; Capoccia, Raffaele ; Narinx, Jonathan ; Baz, Ipek ; Schmid, Alexandre ; Leblebici, Yusuf
Author_Institution :
Microelectron. Syst. Lab. (LSM), Ecole Polytech. Fed. de Lausanne (EPFL) Lausanne, Lausanne, Switzerland
Abstract :
This paper proposes a hardware-oriented trinocular adaptive window size disparity estimation (T-AWDE) algorithm and the first real-time trinocular disparity estimation (DE) hardware that targets high-resolution images with high-quality disparity results. The proposed trinocular DE hardware is the enhanced version of the recently published binocular AWDE implementation. The T-AWDE hardware generates a very high-quality depth map by merging two depth maps obtained from the center-left and center-right camera pairs. The T-AWDE hardware enhances disparity results by applying a double checking scheme which solves most of the occlusion problems existing in the AWDE implementation while providing correct disparity results even for objects located at left or right edge of the center image. The proposed T-AWDE hardware architecture enables handling 55 frames per second on a Virtex-7 FPGA at a 1024×768 XGA video resolution for a 128 pixels disparity range.
Keywords :
estimation theory; field programmable gate arrays; image resolution; real-time systems; DE hardware; T-AWDE algorithm; Virtex-7 FPGA; XGA video resolution; hardware oriented trinocular adaptive window size disparity estimation; image resolution; real-time hardware; real-time trinocular disparity estimation; trinocular DE hardware; trinocular adaptive window size disparity estimation algorithm; Cameras; Computer architecture; Estimation; Field programmable gate arrays; Hardware; Real-time systems; Streaming media; FPGA; Hardware Architecture; Real-Time; Trinocular Disparity Estimation;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114525