Title :
BRAM efficient multi-ported memory on FPGA
Author :
Jiun-Liang Lin ; Lai, Bo-Cheng Charles
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan
Abstract :
Multi-ported memory is broadly used in modern designs on FPGAs. However, the excessive demand on BRAMs to implement multi-ported memory on FPGA would block the usage of BRAMs for other parts of a design. This issue becomes a serious concern especially for designs that require huge internal storage capacity. This paper proposes a BRAM efficient scheme on increasing read ports and write ports. When compared with previous works, the proposed multi-ported memory can reduce up to 53% requirement on BRAMs with only minor frequency degradation.
Keywords :
field programmable gate arrays; logic design; random-access storage; BRAM efficient multiported memory; FPGA design; block RAM; internal storage capacity; read ports; write ports; Clocks; Degradation; Field programmable gate arrays; Frequency division multiplexing; Logic gates; Memory management; Registers; BRAM efficient; FPGA; multi-ported memory;
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-DAT.2015.7114526
