Integrating aging aware timing analysis into a commercial STA tool

With the continuous scaling of transistor sizes, aging effects become more and more pronounced. Two dominant effects are negative bias temperature instability (NBTI) and hot carrier injection (HCI). Both of these mechanisms negatively impact the timing behavior of circuits. Traditionally, aging analysis has not been a part of the established circuit design flow. However, as the impact of aging effects increases, the necessity of their consideration in the design flow grows. Various device and gate level models have been developed to explore and study these effects. However, commercial tools do not yet support aging analysis on gate level, therefore aging analysis is not commonly available to industrial designers yet. This paper presents an automated methodology for fast and accurate NBTI and HCI aware timing analysis. The approach utilizes the AgeGate aging aware gate model and integrates it into a commercial static timing analysis (STA) tool (Synopsys PrimeTime). The paper presents results obtained from applying the method to various benchmark circuits. These results demonstrate that aging is relevant and that it can efficiently be analyzed using commercial tools.