A 60-dB DR PGA with DC-offset calibration for short-distance wireless receiver

Author

Xiaokun Zhao ; Zheng Song ; Baoyong Chi

Author_Institution

Inst. of Microelectron., Tsinghua Univ., Beijing, China

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

4

Abstract

A low-power, high-linearity programmable gain amplifier (PGA) with DC-offset calibration (DCOC) is presented. The PGA has a large gain range from 5dB to 65dB with 1dB step. Benefited from an improved source-degenerated architecture, the measured gain error is less than 0.15dB. By adopting the closed-loop architecture and resistor array optimization, the PGA achieves an OIP3 of 19.2dBm and an output P1dB of 7.58dBm. Two methods are implemented for DC-offset cancellation: RC high-pass filter (HPF) and digital-assisted DCOC. Implemented in TSMC 0.18um process, the PGA occupies 0.37mm² die area and consumes 1.82mA (I and Q path) from a 1.7V supply.

Keywords

RC circuits; amplifiers; calibration; high-pass filters; optimisation; programmable circuits; radio receivers; resistors; DC-offset calibration; DC-offset cancellation:; DR PGA; HPF; OIP3; RC high-pass filter; TSMC process; closed-loop architecture; current 1.82 mA; digital-assisted DCOC; gain 1 dB; gain 5 dB to 65 dB; improved source-degenerated architecture; programmable gain amplifier; resistor array optimization; short-distance wireless receiver; size 0.18 mum; voltage 1.7 V; Calibration; Electronics packaging; Gain; Linearity; Receivers; Resistors; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-DAT.2015.7114572

Filename

7114572