DocumentCode :
710405
Title :
A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems
Author :
Liang-Yu Huang ; Chia-Yi Wu ; Chun-Yi Liu ; Wei-Chang Liu ; Chih-Feng Wu ; Shyh-Jye Jou
Author_Institution :
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear :
2015
fDate :
27-29 April 2015
Firstpage :
1
Lastpage :
4
Abstract :
In this paper, a phase noise cancellation (PNC) architecture is presented for 60 GHz communication systems. The BER performance is severely degraded by the non-ideal carrier frequency in 60 GHz bandwidth, which causes both common phase error (CPE) and residual carrier frequency offset (RCFO). The proposed simplified two-stage CPE algorithm solves the RCFO and common phase nose in the frequency domain and eliminates the constellation rotation on each sub-channel. Two-stage architecture together with deep pipelining technique achieves a high throughput rate. This PNC architecture has been implemented in a SC/OFDM Dual-Mode baseband receiver satisfying the requirements of the 802.15.3c/802.11ad standard with a 40 nm process. The proposed PNC is able to support 64QAM/16QAM for OFDM/SC mode, and can achieve up to 19.2 Giga-bit per second (Gbps) throughput rate at 400 MHz operating frequency with power consumption of 33 mW and area of 0.142 mm2.
Keywords :
OFDM modulation; error statistics; quadrature amplitude modulation; radio receivers; 64QAM/16QAM; 802.15.3c/802.11ad dual mode phase noise cancellation; BER performance; OFDM/SC mode; SC/OFDM dual-mode baseband receiver; bandwidth 60 GHz; bit rate 19.2 Gbit/s; common phase error; communication systems; frequency 400 MHz; phase noise cancellation architecture; power 33 mW; residual carrier frequency offset; size 40 nm; Algorithm design and analysis; Baseband; Bit error rate; Hardware; IEEE 802.15 Standards; OFDM; Phase noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, Automation and Test (VLSI-DAT), 2015 International Symposium on
Conference_Location :
Hsinchu
Type :
conf
DOI :
10.1109/VLSI-DAT.2015.7114575
Filename :
7114575
Link To Document :
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