DocumentCode
710625
Title
Special session: Hot topics: Statistical test methods
Author
Barragan, Manuel J. ; Leger, Gildas ; Azais, Florence ; Blanton, R.D. ; Singh, Adit D. ; Sunter, Stephen
Author_Institution
TIMA, CNRS-Univeristé Grenoble-Alpes, France
fYear
2015
fDate
27-29 April 2015
Firstpage
1
Lastpage
2
Abstract
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as a challenging highly dimensional multivariate problem.
Keywords
Circuit faults; Data mining; Integrated circuit modeling; Radio frequency; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Test Symposium (VTS), 2015 IEEE 33rd
Conference_Location
Napa, CA, USA
Type
conf
DOI
10.1109/VTS.2015.7116265
Filename
7116265
Link To Document