A robust digital sensor IP and sensor insertion flow for in-situ path timing slack monitoring in SoCs

Because of process variations, the post-silicon critical or near-critical paths differ from those identified in the pre-silicon stage. Thus, it has become necessary to extract timing slack information from circuit paths in the post-silicon phase. In this paper, we present a robust digital sensor IP for in-situ timing slack monitoring on actual circuit paths from SoCs. The timing slack data is converted into a digital format and stored in a dedicated scan register chain for easy extraction at any point in time during test and functional modes. A novel layout-aware and netlist-level sensor insertion flow is proposed. The sensor IP has been designed with 32/28nm standard cell library and its performance is demonstrated in the physical design of several benchmark circuits.