Title :
Testing cross wire opens within complex gates
Author :
Chao Han ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
Abstract :
Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in circuits implemented from primitive logic gates, they do not model a type of open fault found only in complex CMOS gates. We refer to these as cross wire open (CWO) faults. In this paper, we develop the first tests that target CWOs. Although we observe that the fault list of potential CWOs can be significantly reduced if the layouts of complex gate cells used in the design are available, we present test generation methodologies both with and without this layout information. CWO fault coverage results for scan based tests are presented for ISCAS89 and ITC99 benchmark circuits that have been resynthesized using an open source cell library containing complex gates.
Keywords :
CMOS logic circuits; fault diagnosis; integrated circuit layout; logic gates; logic testing; CMOS open defects; CWO faults; ISCAS89 benchmark circuits; ITC99 benchmark circuits; TDF timing tests; TSOF; complex CMOS gates; complex gate cells; cross wire open faults; layout information; logic gates; shipped parts; test generation; transistor stuck open faults; volume production data; Circuit faults; Flip-flops; Hazards; Layout; Logic gates; Timing; Wires; complex gates; cross wire opens; open defects;
Conference_Titel :
VLSI Test Symposium (VTS), 2015 IEEE 33rd
Conference_Location :
Napa, CA
DOI :
10.1109/VTS.2015.7116301
