Title :
A new ultra high density 1F1R MLC flash contact RRAM
Author :
Yu-Wen Chung ; Wen Chao Shen ; Ping-Yu Chen ; Zih-Song Wang ; Huei-Haurng Chen ; Ming-Jinn Tsai ; Ya-Chin King ; Chrong Jung Lin
Author_Institution :
Microelectron. Lab., Nat. Tsing-Hua Univ., Hsinchu, Taiwan
Abstract :
A new ultra high-density memory is firstly demonstrated by combining contact random access memory (CRRAM) with flash memory cell as a 1F1R structure. This study reports the first time of processing CRRAM in advanced 50nm flash memory process. The combination of CRRAM and flash cell to form a single Multi-Level Cell (MLC) memory directly doubles the storage capacity without area penalty. The TiON-based resistive film is sandwiched by a tiny tungsten contact plug as a top electrode and source n+ region as a bottom electrode. The new 1F1R MLC memory is successfully realized by two combined storage mechanisms: the contact resistive film switching between HRS and LRS states and the floating gate operating between high and low VTH states. Besides, its excellent reliability of high endurance, stable data retention, and read and program disturb immunity further support this new 1F1R MLC Flash Contact RRAM to be a very promising candidate for high-density NVM applications beyond floating gate solutions.
Keywords :
electrodes; flash memories; metallic thin films; oxygen compounds; resistive RAM; titanium compounds; 1F1R MLC flash contact RRAM; 1F1R structure; CRRAM; MLC memory; TiON; TiON-based resistive film; bottom electrode; contact random access memory; contact resistive film switching; flash memory cell; floating gate; multi-level cell memory; program disturb immunity; size 50 nm; source n+ region; storage capacity; top electrode; tungsten contact plug; ultra high-density memory; Computer architecture; Films; Flash memories; Logic gates; Microprocessors; Nonvolatile memory; Random access memory;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2015.7117557