Title :
III-V nanowire channel on Si: From high-performance vertical FET to steep-slope devices
Author :
Tomioka, Katsuhiro ; Motohisa, Junichi ; Fukui, Takashi
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
MOSFETs using III-V channels with multi-gate architecture and tunnel junctions are promising alternative building blocks for high-performance and low power nanoelectronic circuits. CMOS. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions.
Keywords :
III-V semiconductors; MOSFET; elemental semiconductors; nanoelectronics; nanowires; semiconductor heterojunctions; silicon; tunnel transistors; CMOS; III-V NW heterojunctions; III-V nanowire channel; MOSFET; Si; low power nanoelectronic circuits; multi-gate architecture; silicon heterojunctions; steep-slope devices; surrounding-gate transistors; tunnel junctions; tunneling FET; vertical FET; HEMTs; Heterojunctions; Indium gallium arsenide; Logic gates; Silicon; Tunneling;
Conference_Titel :
VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on
Conference_Location :
Hsinchu
DOI :
10.1109/VLSI-TSA.2015.7117561
