Process integration and 3D chip stacking for low cost backside illuminated CMOS image sensor

Author

Hsiang-Hung Chang ; Zhi-Cheng Hsiao ; Jen-Chun Wang ; Chun-Hsien Chien ; Cheng-Ta Ko ; Chau-Jie Zhan ; Yu-Wei Huang ; Yu-Chen Hsin ; Chung-Chih Wang ; Pei-Jer Tzeng ; Cha-Hsin Lin ; Chia-Hsin Lee ; Ting-Sheng Chen ; Wei-Chung Lo ; Tzu-Kun Ku ; Yung-Fa Cho

Author_Institution

Electron. & Optoelectron. Res. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2015

fDate

27-29 April 2015

Firstpage

1

Lastpage

2

Abstract

A novel low cost backside illuminated CMOS image sensor structure is proposed in this research. By using thin wafer handling technology, the wafer is thinned down to less than 5 μm and no TSV and direct bonding process are needed in this low cost solution. The processed backside illuminated CMOS image sensor is then stacked with analog to digital conversion chip and image signal processor by 3DIC technology. A 3-Mega pixel image is captured and demonstrated in this research.

Keywords

CMOS image sensors; analogue-digital conversion; digital signal processing chips; three-dimensional integrated circuits; 3D IC technology; 3D chip stacking; TSV; analog to digital conversion chip; direct bonding process; image signal processor; low cost backside illuminated CMOS image sensor; process integration; thin wafer handling technology; through-silicon-via; Bonding; CMOS image sensors; Dry etching; Stacking; Three-dimensional displays;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Application (VLSI-TSA), 2015 International Symposium on

Conference_Location

Hsinchu

Type

conf

DOI

10.1109/VLSI-TSA.2015.7117587

Filename

7117587