D8. Low power pseudo CMOS memory cell for matrix ROM applications

In this paper, a low power pseudo CMOS inverter for matrix ROM realization is presented. The proposed circuit consists of grounded gate pulled up pMOST and a conventional CMOS inverter in cascaded. Thus, the proposed cell is suitable for low power circuit referred to the conventional pseudo inverter. The free hand designed equations are driven based on square law MOSFET model. The presented inverter is used for representing the memorized data 1 or 0, which is the ROM memory basic element. The designed cell features great saving of power consumption at least 33%, and provides high performance. The proposed pseudo-CMOS inverter consumed power less than 20μW/cell using 1.5-supply voltage, and it is designed and simulated using the IBM 130nm CMOS technology.