A 1.8 to 2.4 GHz stacked power amplifier implemented in 0.25/SPL mu/m CMOS SOS technology

Author

Helmi, Sultan R. ; Hengying Shan ; Mohammadi, Saeed

Author_Institution

Purdue Univ., West Lafayette, IN, USA

fYear

2015

fDate

26-28 Jan. 2015

Firstpage

52

Lastpage

54

Abstract

A fully-integrated power amplifier (PA) designed with 8 stacked transistors is implemented in a 0.25/SPL mu/m Ultra-CMOS Silicon-on-Sapphire (SOS) technology. The stacked Cascode configuration allows the PA to deliver high gain and high output power while maintaining the PA stability. At 2.2 GHz, the PA under a bias supply of 16 V (2V per transistor) measures a saturated output power PSAT of 28.5 dBm (0.7 Watt) and a linear gain of 21.7 dB with a peak power-added efficiency (PAE) and drain efficiency (DE) of 16% and 18.5%, respectively. PAE and DE increase to 25.5% and 29%, respectively, when the PA is biased with a 13 V power supply. In the frequency range of 1.8 to 2.4 GHz the PSAT was above 27.6 dBm.

Keywords

CMOS integrated circuits; UHF integrated circuits; UHF power amplifiers; integrated circuit design; silicon-on-insulator; 8-stacked transistors; CMOS SOS technology; PA stability; drain efficiency; efficiency 25.5 percent; efficiency 29 percent; frequency 1.8 GHz to 2.4 GHz; fully-integrated power amplifier design; gain 21.7 dB; linear gain; peak power-added efficiency; saturated output power; size 0.25 mum; stacked cascode configuration; stacked power amplifier; ultraCMOS silicon-on-sapphire technology; voltage 13 V; voltage 16 V; CMOS integrated circuits; CMOS technology; Gain; Power amplifiers; Power generation; Transistors; Voltage measurement; CMOS; Radio Frequency; SOS; stacked power amplifiers;

fLanguage

English

Publisher

ieee

Conference_Titel

Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2015 IEEE 15th Topical Meeting on

Conference_Location

San Diego, CA

Type

conf

DOI

10.1109/SIRF.2015.7119872

Filename

7119872