DocumentCode :
711858
Title :
Memory Coherency Based CPU-Cache-FPGA Acceleration Architecture for Cloud Computing
Author :
Hao Yang ; Xiaolang Yan
Author_Institution :
Inst. of VLSI Design, Zhejiang Univ., Hangzhou, China
fYear :
2015
fDate :
24-26 April 2015
Firstpage :
304
Lastpage :
307
Abstract :
The power efficiency target is becomes the first goal of current hardware system. The workload under cloud computing environment needs to be accelerated by hardware as more as possible, in order to improve the overall power/performance efficiency. The traditional CPU-FPGA architecture can not handle fine granularity routine of algorithm by FPGA hardware in a effective way, as well as challenge on programming model. This paper proposed a memory/cache coherency based CPU-Cache-FPGA architecture to perform an effective transparent communication between software threads on CPU and hardware threads on FPGA. In a sorting application example, the proposed architecture can gain 2.6 times acceleration ratio than traditional CPU-FPGA architecture, as well as a simplified programming model.
Keywords :
cache storage; cloud computing; field programmable gate arrays; power aware computing; acceleration ratio; cloud computing environment; hardware threads; memory coherency based CPU-cache-FPGA acceleration architecture; power efficiency; simplified programming model; software threads; transparent communication; Control engineering; Information science; Acceleration; FPGA; Memory Coherency; Share Memory;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Information Science and Control Engineering (ICISCE), 2015 2nd International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4673-6849-0
Type :
conf
DOI :
10.1109/ICISCE.2015.74
Filename :
7120614
Link To Document :
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