Memory Prefetcher Design Based on the SESC Simulator

Author

Liu Fang ; Zhang Shengbing ; Zhao Lei ; Zhang Meng

Author_Institution

Sch. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xi´an, China

fYear

2015

fDate

24-26 April 2015

Firstpage

308

Lastpage

312

Abstract

A system-level architecture simulator can be used as a virtual target machine, which can achieve the functional and detail simulation of a system composed of a processor, a system memory, caches, and external devices. Perfecting technology can improve the overall performance of the system by reducing pipeline stalls according to the temporal and spatial locality. This article is based on the characteristics of multi-core processors to study the design method of architectural simulators. We use an architecture simulator to evaluate the requirements of memory system based on different architecture and achieve two prefetchers, as well as test the prefetcher´s impact on bandwidth.

Keywords

multiprocessing systems; storage management; virtual machines; SESC simulator; Super Escalar Simulator; architectural simulators; event-driven simulator; memory prefetcher design; multicore processors; Bandwidth; Hardware; Markov processes; Memory management; Multicore processing; Prefetching; SESC; memory prefetcher; prefetching performance; system-level architecture simulator;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Science and Control Engineering (ICISCE), 2015 2nd International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4673-6849-0

Type

conf

DOI

10.1109/ICISCE.2015.75

Filename

7120615