Title :
Challenges in implementing high-speed, low-power ADCs in CMOS
Author_Institution :
IBM Res. - Zurich, Zurich, Switzerland
Abstract :
Challenges of CMOS ADC implementations for 100 Gb/s optical communication systems and beyond are highlighted. Limitations and opportunities of architectures and circuits are discussed based on a 56-90 GS/s 8 bit ADC in 32 nm SOI CMOS.
Keywords :
CMOS integrated circuits; analogue-digital conversion; optical communication; SOI CMOS; bit rate 100 Gbit/s; high-speed low-power ADC; optical communication systems; Bandwidth; CMOS integrated circuits; Clocks; Frequency measurement; Optical fiber communication; Optical switches; Power demand;
Conference_Titel :
Optical Fiber Communications Conference and Exhibition (OFC), 2015
Conference_Location :
Los Angeles, CA
