Performance study of high-k gate & spacer dielectric Dopant Segregated Schottky Barrier SOI MOSFET

In this paper, a comprehensive study on the performance of Dopant Segregated Schottky Barrier Silicon-on-Insulator (DSSB-SOI) MOSFETs with high-k (HfO₂)gate & spacer dielectric is presented. High-k dielectric is extensively used for nanoscale device performance improvement, due to it sreduced off state leakage and enhanced electrostatic control over the channel. It has been found that, due to the presence of high-k dielectric, the major short channel device constraints subthreshold slope and off state leakage is reduced as compared to conventional DSSB SOI MOSFET having low-k(SiO₂) gate and spacer dielectric. A strong impact of SOI thickness, channel length, on the performance of proposed DSSB SOI MOSFET are observed using SilvacoATLAS 2D device Simulator. The proposed device achieves higher I_on/I_off (>10⁵) &I_off <; 10¹⁰A/μm.