Variation of power dissipation for Adiabatic CMOS and conventional CMOS digital circuits

From the past few decades, VLSI technologyhas been growing to the large extent. All credit for this goes to the increasing usage of integrated circuits for every embedded system, mobile technologies, computing systems, etc. Increasing growth and use of technology has increased the thirst for low energy or power consumption. An Adiabatic approach is perfect solution for the designing of power and energy efficient designs. The word `Adiabatic´ refers to the change of state that occurs without the loss or gain of heat. This paper studies low power design techniques and justifies the need of energy recovery adiabatic circuits over conventional CMOS. The logic circuits based on traditional CMOS Logic and positive feedback Adiabatic Logic will be designed and simulated using standard 90nm CMOS technology at a frequency of 50MHz. Tanner EDA tool is used for designing the schematic and analysis. The S-EDIT is used to design the schematic and T-SPICE is used to Simulate and check the results of Power Dissipation. W-EDIT is used to display the simulation results in the form of waveform.