An event based CMOS quad bilateral combination with asynchronous SRAM architecture based neural network using low power

Neural networks have a wide range of applications in analog and digital signal processing. Once the network has been trained and the synaptic weight values stored in the SRAM, the VLSI device can be used in stand-alone mode to carry out neural computation in real-time. In existing system they implemented the neural network with programmable synaptic memory. Synaptic weight refers to the strength of a connection between two nodes. The design of neural network architecture is based on CMOS technology and the design performed in its architecture level. Commonly CMOS technology provides less noise during design. The proposed neural network consists of Synaptic weight and spiking network. In the existing system, they concentrated only in spike frequency and spike voltage. The proposed system focuses on reducing the complexity and increasing the efficiency and the network using CMOS technology with quad bilateral technique used in integrated circuit designed to reduce power consumption, by shutting off the current to block the circuits that are not in use and also multiple threshold voltages applied to the circuit which helps to reduce the delay/power. In addition to reducing standby or leakage power this approach eliminates critical path delay. The proposed design concentrates on reducing complexity; hence the power consumption will be reduced. And also efficiency will be increased due to less complexity. The proposed system is used in image processing & control system applications.