Hardware implementation of a background substraction algorithm in FPGA-based platforms

Author

Calvo-Gallego, Elisa ; Sanchez-Solano, Santiago ; Brox Jimenez, Piedad

Author_Institution

Inst. de Microelectron. de Sevilla (IMSE-CNM), Univ. of Seville, Seville, Spain

fYear

2015

fDate

17-19 March 2015

Firstpage

1688

Lastpage

1693

Abstract

Different strategies for the implementation of a fuzzy logic-based background subtraction algorithm are presented in this paper. The goal of this contribution is to obtain an efficient implementation suitable to be integrated into hardware platforms with limited resources. In order to find an adequate performance-resources trade-off, the design space is explored taken into account several strategies and implementation options. The final implementation is encapsulated within an IP core that has been used in a demonstrator, built on a Spartan-3A-DSP FPGA development board, suitable for processing VGA (640×480P) @ 60 Hz.

Keywords

field programmable gate arrays; fuzzy logic; IP core; Spartan-3A-DSP FPGA development board; background substraction algorithm; demonstrator; design space; frequency 60 Hz; fuzzy logic-based background subtraction algorithm; hardware implementation; hardware platforms; performance-resources trade-off; Algorithm design and analysis; Approximation algorithms; Field programmable gate arrays; Hardware; Heuristic algorithms; Power demand; Random access memory; background substraction; foreground extraction; fuzzy logic-based techniques; hardware implementation;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial Technology (ICIT), 2015 IEEE International Conference on

Conference_Location

Seville

Type

conf

DOI

10.1109/ICIT.2015.7125340

Filename

7125340