A networking EDA tool for multi-vector multiplication IP circuits

Engineering teams all over the globe are facing daunting tasks in the design of system components in the contemporary multi-billion transistor era. Even though there are EDA tools to generate intellectual property (IP) blocks for many circuits, to the best of our knowledge, there are no tools to design IP blocks of multi-vector multiplication units, which are required in order to design hardware solvers for linear systems and eigenvalue problems. We noticed this absence and we designed a tool to create verified HDL description of such circuits and furthermore, we have made it available via our public web server. Our IP blocks are vendor neutral and can be synthesized either on ASIC or on FPGA. Our synthesized circuits on Xilinx Virtex 6 FPGA, operate up to 589 Mhz.