A heuristic algorithm for high level synthesis of decimal arithmetic circuits using SystemC

High level synthesis has proven to be an effective approach to handle the complexity of today´s system designs. This is particularly true when it comes to designing large systems that incorporate specialized hardware for specific applications such as decimal arithmetic. In this paper, a heuristic algorithm is presented that takes high level description of arithmetic circuits and explores the design space in order to find an implementation with minimum area under delay constraint. To provide the necessary language support for high level description of arithmetic operations, an extension of SystemC is proposed. The proposed algorithm considers possible implementations using an extended library of high-level arithmetic modules and finds the one that optimizes an objective (area) under some constraints (delay).