Effect of Annealing on Defect Elimination for High Mobility Amorphous Indium-Zinc-Tin-Oxide Thin-Film Transistor

Author

Chur-Shyang Fuh ; Po-Tsun Liu ; Wei-Hsun Huang ; Sze, Simon M.

Author_Institution

Dept. of Electron. EngineeringInstitute of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

35

Issue

11

fYear

2014

fDate

Nov. 2014

Firstpage

1103

Lastpage

1105

Abstract

This letter studies the correlation of postannealing treatment on the electrical performance of amorphous In-Zn-Sn-O thin-film transistor (a-IZTO TFT). The 400 °C annealed a-IZTO TFT exhibits a superior performance with field-effect mobility of 39.6 cm²/Vs, threshold voltage (Vth) of -2.8 V, and subthreshold swing of 0.25 V/decade. Owing to the structural relaxation by 400 °C annealing, both trap states of a-IZTO film and the interface trap states at the a-IZTO/SiO₂ interface decrease to 2.16×10¹⁷ cm^-3eV^-1 and 4.38×10¹² cm^-2 eV^-1, respectively. The positive bias stability of 400 °C annealed a-IZTO TFTs is also effectively improved with a V_th shift of 0.92 V.

Keywords

amorphous semiconductors; annealing; indium compounds; thin film transistors; tin compounds; zinc compounds; In-Zn-Sn-O; a-IZTO TFT; a-IZTO film; a-IZTO-SiO2 interface; defect elimination; electrical performance; high mobility amorphous In-Zn-Sn-O thin-film transistor; interface trap states; postannealing treatment; temperature 400 C; voltage -2.8 V; voltage 0.92 V; Annealing; Logic gates; Performance evaluation; Substrates; Thermal stability; Thin film transistors; In-Zn-Sn-O TFTs; high mobility TFTs;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/LED.2014.2354598

Filename

6899612