• DocumentCode
    715915
  • Title

    A low capture power test generation method using capture safe test vectors

  • Author

    Hirai, Atsushi ; Hosokawa, Toshinori ; Yamauchi, Yukari ; Arai, Masayuki

  • Author_Institution
    Grad. Sch. of Ind. Technol., Nihon Univ., Chiba, Japan
  • fYear
    2015
  • fDate
    25-29 May 2015
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    In this paper, we propose a new low capture power test generation method based on fault simulation to reduce the number of unsafe faults. The method uses capture-safe test vectors in an initial test set to generate new test vectors. Our experimental results show that the use of this method reduces the number of unsafe faults by 94% on average, and while requiring less test generation time compared with the conventional low capture power test generation method.
  • Keywords
    fault simulation; low-power electronics; capture safe test vectors; fault simulation; power test generation method; Benchmark testing; Central Processing Unit; Circuit faults; Europe; Fault diagnosis; Switches; capture-safe test vectors; low power; test generation; test vector synthesis; unsafe faults;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ETS), 2015 20th IEEE European
  • Conference_Location
    Cluj-Napoca
  • Type

    conf

  • DOI
    10.1109/ETS.2015.7138740
  • Filename
    7138740