Designing area-efficient controllers for multi-cycle transient fault tolerant systems

This paper discusses a controller design in high-level synthesis to tolerate multi-cycle transient faults under the situation where its datapath has the ability of tolerating such faults. It focuses especially on the control signal generator (or output logic) that is a component of the controller feeding control signals to the datapath in a controller-datapath system, and presents a method of controller synthesis that leverages the error correction/detection ability of the datapath. Experimental results show that the proposed method can synthesize fault tolerant controllers with small area overhead compared with the conventional method based on triple modular redundancy (TMR).