Automatic generation of autonomous built-in observability structures for analog circuits

In this paper a new method is presented to automatically generate a Design-for-Testability infrastructure which increases the observability of defects in integrated circuits. An algorithm is proposed to detect circuit locations to which small detection blocks can be added. Those are coupled to an oscillator and the triggering of this oscillator in case of detected defects leaves traces in the power consumption. Therefore, the detection of a defective circuit can directly be transmitted to the Automated Test Equipment without requiring a special routing of the signals on the chip and extra test pins. Simulations on an industrial circuit show a 86 percent fault coverage of the hard-to-detect faults for an area increase of less than a percent.