Compact test set generation for test compression-based designs

The manufacturing test is an important and expensive part of the overall electronic design flow. A main cost factor is the steadily increasing test data volume. Modern designs typically use extra hardware, i.e. test compression hardware, to compress the scan patterns to save test data volume. However, this imposes constraints on the pattern generation process. A high number of unspecified bits is typically needed to compress a test pattern successfully. In this paper, a compact test set generation technique is proposed for test compression-based designs. The proposed technique is based on a fully-specified test set and uses test vector decomposition, multiple-fault-detection and atomic vector ordering in order to build a highly compact test set with a guaranteed percentage of unspecified bits. Experimental results on benchmark and industrial circuits show that the approach is able to achieve a significant pattern reduction compared to previous approaches. Furthermore, it is shown that a higher compaction of the basis test set leads to a higher compaction of the resulting partially-specified test set.