DocumentCode
717156
Title
Hardware accelerated flow measurement of 100 Gb ethernet
Author
Pus, Viktor ; Velan, Petr ; Kekely, Lukas ; Korenek, Jan ; Minarik, Pavel
Author_Institution
CESNET, z.s.p.o., Prague, Czech Republic
fYear
2015
fDate
11-15 May 2015
Firstpage
1147
Lastpage
1148
Abstract
This demo demonstrates results of a joint research project of CESNET and INVEA-TECH focused on 100 GbE network flow monitoring using FPGA. It shows, to the best of our knowledge, the first flow monitoring setup capable of handling fully saturated 100 G Ethernet line. We present COMBO-CG card that provides accurate timestamps for high-resolution traffic monitoring. The card is complemented by fast DMA engine and optimized Linux drivers which were designed and implemented to achieve 100 Gbps data transfers through PCIe bus with low CPU utilization. Network traffic can be distributed among multiple CPU cores based on configurable hash functions. Our flow exporter is able to fully utilize available CPU cores to provide wire-speed performance for processing of the 100 Gbps traffic. The demo will show complete 100 G flow monitoring setup - from packet generator to flow collector.
Keywords
Linux; cryptography; field programmable gate arrays; file organisation; flow measurement; local area networks; telecommunication traffic; CESNET; COMBO-CG card; Ethernet line; FPGA; INVEA-TECH; Linux drivers; PCIe bus; bit rate 100 Gbit/s; configurable hash functions; fast DMA engine; flow collector; hardware accelerated flow measurement; high-resolution traffic monitoring; low CPU utilization; multiple CPU cores; network flow monitoring; packet generator; timestamps; wire-speed performance; Central Processing Unit; Data transfer; Field programmable gate arrays; Generators; Hardware; Monitoring; Throughput;
fLanguage
English
Publisher
ieee
Conference_Titel
Integrated Network Management (IM), 2015 IFIP/IEEE International Symposium on
Conference_Location
Ottawa, ON
Type
conf
DOI
10.1109/INM.2015.7140452
Filename
7140452
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