Fault Current Testing Envelopes for VSC HVDC Circuit Breakers

Circuit breakers for High Voltage Direct Current (HVDC) are seen as a required technological step in the development of HVDC grids. The development of several new HVDC circuit breaker prototypes indicate that this step may be achieved in the years to come. In order to facilitate the installation of HVDC circuit breakers, appropriate standards and tests need to be developed. These tests and standards must ensure that the technology is capable of functioning as required. In cases where direct testing cannot be carried out, a synthetic test circuit is used to recreate the conditions of the power system. Voltage testing envelopes are used to define the specification of these synthetic test circuits for Alternating Current (AC) circuit breakers. A similar concept can be applied to fault currents in HVDC networks, allowing specifications for HVDC synthetics test circuits to be defined. Testing envelopes which encapsulate the fault currents are analytically shown in this paper and compared to detailed simulations of faults in a VSC HVDC system. Testing envelopes can be drawn for a range of converter topologies in point-to-point and multi-terminal applications. Taking into account the large power electronic elements in the recently developed HVDC circuit breakers, discussion is given to the definition the worst case fault for a HVDC protection system. This paper demonstrates that a terminal fault is not necessarily the worst fault scenario for HVDC circuit breaker.