Power Performance Analysis of the Iterative-MIMO Adaptive Switching Algorithm Detector on the FPGA Hardware

In this paper, a comprehensive power performance analysis of a novel Adaptive Switching Algorithm for an iterative-MIMO system is investigated with the prime goal of minimizing energy consumption in the receiver. The algorithm works by switching between a high performance detection method, the Fixed Sphere Decoding, and a much lower complexity algorithm, the Vertical-Bell Laboratories Layered Space-Time Zero Forcing technique, controlled by a threshold according to the mutual information calculated during each transmission. Results show significant improvements over current non-adaptive receivers, where energy savings of more than 60% can be obtained using on the latest Xilinx^®Virtex-7 FPGA hardware.