A new Nano-scale differential logic style for power analysis attack

Power analysis of a circuit depends heavily to its individual transistors activity. Measuring the consumed power of an actual chip can be used to extract the internal data of the chip. This matter becomes more noteworthy once secure implementations like cryptographic modules are considered. In this paper, a new Nano-scale differential logic style is proposed which is robust against differential power analysis attack. The proposed technique is compared with the similar logic styles such as SABL, TDPL, STDPL and 3sDDL in terms of normalized energy deviation (NED). Simulation results show that NED is reduced at least by 200%. However the proposed logic style burdens some overheads in terms of number of transistors and maximum power consumptions as well.