DocumentCode :
718074
Title :
A new linear delay element with self calibration
Author :
Seraj, Afshin ; Maymandi-Nejad, Mohammad ; Sachdev, Manoj
Author_Institution :
Electr. Eng. Dept., Ferdowsi Univ. of Mashhad (FUM), Mashhad, Iran
fYear :
2015
fDate :
10-14 May 2015
Firstpage :
1050
Lastpage :
1053
Abstract :
Linearity in Delay Element is an important factor in many applications such as Fully Digital Analog to Digital Converters, Delay-Locked-Loops and Voltage Controlled Oscillators. In this work, a new Delay Element is proposed in which the relationship between the input analog voltage and the delay between its input pulse and output pulse is highly linear within an analog voltage range of 0.9V and a delay range of 0.5ns-4.5ns. The proposed Delay Element has been simulated using H-spice with a supply voltage of 1.8V in the 0.18 um CMOS technology. A calibration mechanism based on feedback technique is also proposed which can be used to reduce the impact of PVT variations.
Keywords :
CMOS integrated circuits; SPICE; calibration; delay lines; delay lock loops; digital-analogue conversion; voltage-controlled oscillators; CMOS; H-spice; PVT; delay-locked-loops; digital analog to digital converters; linear delay element; self calibration; size 0.18 mum; time 0.5 ns to 4.5 ns; voltage 0.9 V; voltage 1.8 V; voltage controlled oscillators; Conferences; Electrical engineering; PVT variations; delay line; delay locked loop; fully digital ADC; linear; self calibration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electrical Engineering (ICEE), 2015 23rd Iranian Conference on
Conference_Location :
Tehran
Print_ISBN :
978-1-4799-1971-0
Type :
conf
DOI :
10.1109/IranianCEE.2015.7146366
Filename :
7146366
Link To Document :
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