A new low-power SRAM block suitable for applications with normal data distribution

In this paper, a new algorithm for writing data to and reading data from SRAM is presented. This algorithm reduces switching on read bit-lines by reversible conversion on pattern of input data without any reduction in memory capacity, and decreases write failure and write delay for normally distributed data. An 8T SRAM cell from our previous work was used in the SRAM block. Due to single ended read operation in our cell, an external circuit is posited to increase the number of "1"s at storage nodes. According to sign-bit of input data, the decision is made about how data should be saved to increase the number of "0"s at left internal nodes of SRAM cells that is equal to storing "1" at right internal nodes. To verify the proposed design, a 64×16 SRAM array without external circuits is simulated in 90nm industrial CMOS technology at different supply voltages (typical corner, T=27°C). Simulation results show that power reduction for any normal data distribution depends on standard deviation of data. The results indicate 87.84% power reduction for theoretical systolic blood pressure, and at least 81.84% for average weights of typical age groups of interest in U.S.