Title :
Design of CAD ASIP for JIT extensible processor: Case study on PathFinder routing algorithm
Author :
Daryanavard, Hassan ; Eshghi, Mohammad ; Jahanian, Ali
Author_Institution :
Shahid Beheshti Univ., Tehran, Iran
Abstract :
Just-In-Time (JIT) Extensible Processor is the most flexible platform among others reconfigurable computing platforms. In this platform all computing intensive kernels can be translated to bitstream by embedded CAD processor to be executed on hardware part. Executing CAD algorithms on embedded processor is a time-consuming task and normally is not feasible for real user applications. In this paper, the design of an application-specific instruction set processor (ASIP) has been proposed as a promising solution to speed up the execution time of CAD algorithm used in JIT extensible processor. The proposed ASIP is customized for routing which is one of most time consuming phases. Simplescalar simulator toolset is used to provide high flexible performance processor architecture and adding new extracted instruction set and customized register file and memory to processor. Regarding this specification, we achieved 10X speedup for routing phases.
Keywords :
CAD; application specific integrated circuits; embedded systems; instruction sets; just-in-time; microprocessor chips; network routing; ASIP; CAD ASIP design; CAD embedded processor architecture; JIT extensible processor; application-specific instruction set processor; computing intensive kernels; just-in-time extensible processor; pathfinder routing algorithm; reconfigurable computing platform; Conferences; Decision support systems; Design automation; Electrical engineering; Field programmable gate arrays; Routing; Wires; Application Specific Instruction Set Processor; Just-In-Time Extensible Processor; PathFinder Routing; Simplescalar;
Conference_Titel :
Electrical Engineering (ICEE), 2015 23rd Iranian Conference on
Conference_Location :
Tehran
Print_ISBN :
978-1-4799-1971-0
DOI :
10.1109/IranianCEE.2015.7146421