Ultra low-power 7T SRAM cell design based on CMOS

Author

Moghaddam, Majid ; Moaiyeri, Mohammad Hossein ; Eshghi, Mohammad

Author_Institution

ECE Dept., Shahid Beheshti Univ., Tehran, Iran

fYear

2015

fDate

10-14 May 2015

Firstpage

1357

Lastpage

1361

Abstract

In his paper a 7T SRAM cell operating well in low voltages is presented. Suitable read operation structure is provided by controlling the drain induced barrier lowering (DIBL) effect and body-source voltage in the hold `1´ state. The read-operation structure of the proposed cell utilizes the single transistor which leads to a larger write margin. The simulation results at 90nm TSMC CMOS demonstrate the outperforms of the proposed SRAM cell in terms of power dissipation, write margin, sensitivity to process variations as compared with the other most efficient low-voltage SRAM cells.

Keywords

CMOS memory circuits; SRAM chips; low-power electronics; DIBL effect; TSMC CMOS; body-source voltage; drain induced barrier lowering effect; power dissipation; process variations sensitivity; read operation structure; single transistor; size 90 nm; ultra low-power 7T SRAM cell; write margin; CMOS integrated circuits; Logic gates; SRAM cells; Stability analysis; Threshold voltage; Transistors; DIBL effect; Ultra low power; process variations; write margin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical Engineering (ICEE), 2015 23rd Iranian Conference on

Conference_Location

Tehran

Print_ISBN

978-1-4799-1971-0

Type

conf

DOI

10.1109/IranianCEE.2015.7146428

Filename

7146428