• DocumentCode
    718621
  • Title

    Verification of timed Finite State Machines

  • Author

    Kidyarova, Galina ; Yevtushenko, Nina

  • Author_Institution
    Tomsk State Univ., Tomsk, Russia
  • fYear
    2015
  • fDate
    21-23 May 2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    In this paper, a method is proposed for checking whether two timed Finite State Machines (TFSMs) are equivalent. In the second part of the paper, TFSMs are represented as logic circuits and correspondingly, the verification problem is reduced to their scalable representations where the SAT-solving problem can be efficiently used.
  • Keywords
    finite state machines; logic circuits; SAT-solving problem; TFSM; logic circuit; timed finite state machine; verification problem; Automata; Boolean functions; Combinational circuits; Delay effects; Delays; Sequential circuits; SAT-solving; logic circuit; timed Finite State Machine; verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Control and Communications (SIBCON), 2015 International Siberian Conference on
  • Conference_Location
    Omsk
  • Print_ISBN
    978-1-4799-7102-2
  • Type

    conf

  • DOI
    10.1109/SIBCON.2015.7147095
  • Filename
    7147095
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=718621