A 14-bit 50-MS/s pipelined analog-to-digital converter with digital error calibration

Author

Piatak, Ivan ; Pilipko, Mikhail ; Morozov, Dmitry

Author_Institution

Dept. of the Integrated Electron., Peter the Great St. Petersburg Polytech. Univ., St. Petersburg, Russia

fYear

2015

fDate

21-23 May 2015

Firstpage

1

Lastpage

4

Abstract

A 14-bit 50-MS/s pipelined analog-to-digital converter (ADC) is presented. Operational amplifier (op-amp) sharing technique, 1.5 bit redundant stages based on switched capacitor circuits with inverter-based comparators and digital gain error calibration are used to reduce power consumption of the ADC and relax op-amp requirements. Simulation results in MATLAB/Simulink (structure level) and Cadence Virtuoso (schematic level, 180 nm 1.8 V CMOS) are provided. The pipelined ADC achieves 70 dB SINAD/80 dB SFDR and consumes 135 mW at 1.8 V supply, FoM is 1.04 pJ/conv.

Keywords

CMOS integrated circuits; analogue-digital conversion; comparators (circuits); operational amplifiers; switched capacitor networks; analog-to-digital converter; digital gain error calibration; inverter-based comparators; operational amplifier sharing technique; power 135 mW; size 180 nm; switched capacitor circuits; voltage 1.8 V; CMOS integrated circuits; Calibration; Gain; MATLAB; Mathematical model; Pipelines; Power demand; 1.5 bit redundant stage; CMOS inverter; SC-circuit; comparator; digital error calibration; multiplying DAC; operational amplifier; pipelined ADC;

fLanguage

English

Publisher

ieee

Conference_Titel

Control and Communications (SIBCON), 2015 International Siberian Conference on

Conference_Location

Omsk

Print_ISBN

978-1-4799-7102-2

Type

conf

DOI

10.1109/SIBCON.2015.7147185

Filename

7147185