DocumentCode
718707
Title
The mathematical model of noise characteristics of a direct digital synthesizer with the built-in multiplier of clock frequency on PLL
Author
Romashov, V.V. ; Romashova, L.V. ; Doctorov, A.N.
Author_Institution
Dept. of Radio Eng., Vladimir State Univ., Murom, Russia
fYear
2015
fDate
21-23 May 2015
Firstpage
1
Lastpage
5
Abstract
Direct digital synthesizers with the built-in multipliers of clock frequency are investigated in the article. The mathematical model of power spectral density of phase noise is received, noise characteristics of integrated direct digital synthesizer are investigated, comparison with experimental characteristics is carried out.
Keywords
clocks; digital phase locked loops; direct digital synthesis; multiplying circuits; phase noise; PLL; built-in multiplier; clock frequency; integrated direct digital synthesizer; mathematical model; noise characteristics; phase noise; power spectral density; Clocks; Frequency synthesizers; Mathematical model; Phase locked loops; Phase noise; Synthesizers; Direct digital synthesizer (DDS); Phase Lock Loops (PLL); power spectral density (PSD) of phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
Control and Communications (SIBCON), 2015 International Siberian Conference on
Conference_Location
Omsk
Print_ISBN
978-1-4799-7102-2
Type
conf
DOI
10.1109/SIBCON.2015.7147197
Filename
7147197
Link To Document