DocumentCode :
718992
Title :
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures
Author :
Chillarige, S. ; Virdi, S. ; Malik, A. ; Chakravadhanula, K. ; Chickermane, V. ; Swenton, J. ; Vandling, G.
Author_Institution :
Encounter Test R&D, Cadence Design Syst., Noida, India
fYear :
2015
fDate :
11-13 May 2015
Firstpage :
43
Lastpage :
48
Abstract :
This paper presents a novel approach for performing diagnosis in test access mechanisms (TAM) architectures based on time domain multiplexing and serial scan shifting. These TAM architectures allow efficient application of low power compressed patterns to individual embedded cores present in SoCs using limited pins. The proposed diagnosis approach relies on the connectivity information of the TAM architecture to map SoC level failures to a particular embedded core. These TAM architectures allow high level of diagnosis resolution and performance.
Keywords :
integrated circuit design; integrated circuit testing; system-on-chip; SoC; failure diagnosis; low power compression architectures; serial scan shifting; test access mechanisms architectures; time domain multiplexing; Accuracy; Circuit faults; Feeds; Pins; System-on-chip; Testing; Time division multiplexing; dft silicon diagnosis TAM;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Workshop (NATW), 2015 IEEE 24th North Atlantic
Conference_Location :
Johnson City, NY
Print_ISBN :
978-1-4673-7416-3
Type :
conf
DOI :
10.1109/NATW.2015.17
Filename :
7147653
Link To Document :
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