An effective design of high performance dynamic feed through logic and noise tolerance circuits

This paper gives a new idea for high performance Arithmetic circuits with a new dynamic logic known as feed through logic (FTL). Feed through logic can improve the performance by pre evaluation in its computational block especially for those circuits with high logic depth. An NMOS mirror technique has been introduced to get a better noise tolerance as compared with its predecessors. A 2 input NAND gate with the modified design is simulated by 180 nm UMC CMOS technology. The proposed model achieves an improvement in ANTE by 2.32 times and also in leakage power reduction.